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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">ACTLR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></div></div></div>
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<p>Bit field declaration for ACTLR layout.  
 <a href="unionACTLR__Type.html#details">More...</a></p>

<p><code>#include &lt;core_ca.h&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a901f974f72e3eff281b105681448efa2"><td class="memItemLeft" >struct {</td></tr>
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<tr class="memdesc:abd842b7633adcb3974886e8d18d3217e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast  <a href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">More...</a><br /></td></tr>
<tr class="separator:abd842b7633adcb3974886e8d18d3217e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:a6048faebb4f5c52a1d70a5cfeadea764"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:a4c262c9460a2f9b3a650c49d3197e9eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior  <a href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">More...</a><br /></td></tr>
<tr class="separator:a4c262c9460a2f9b3a650c49d3197e9eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:a790df99d70a7dde618a0750c4d25c589"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:a7029b0e1b69a1d4b129929621090e03e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:a58087740cab37223baa85d735aad9ede"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:a7d6f159fd8af9574fcc64b8bfb7cd00f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:afa20e797af0c7e17b9a06cec0595e144"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a901f974f72e3eff281b105681448efa2"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a901f974f72e3eff281b105681448efa2">b</a></td></tr>
<tr class="memdesc:a901f974f72e3eff281b105681448efa2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A5.  <br /></td></tr>
<tr class="separator:a901f974f72e3eff281b105681448efa2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00823a9d14d51b1d277e95916eaf9302"><td class="memItemLeft" >struct {</td></tr>
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<tr class="memdesc:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6 Enables coherent requests to the processor  <a href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">More...</a><br /></td></tr>
<tr class="separator:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior  <a href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">More...</a><br /></td></tr>
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<tr class="memdesc:adcfdb03d626161678908935ba232830d"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 11 L2 Data Cache read-allocate mode disable  <a href="unionACTLR__Type.html#a947f73d64ebde186b9416fd6dc66bc26">More...</a><br /></td></tr>
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<tr class="memdesc:a473b5ba32637965efc11c81809e2b3e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit:13..14 L1 Data prefetch control  <a href="unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c">More...</a><br /></td></tr>
<tr class="separator:a473b5ba32637965efc11c81809e2b3e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:a9d6ad195b1b4f3887393a54a595a9124"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 15 Disable Distributed Virtual Memory (DVM) transactions  <a href="unionACTLR__Type.html#a4fe04e95b26e089642bee6952f223f82">More...</a><br /></td></tr>
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<tr class="memdesc:a48784073516f219c76ac50a89973dc78"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 Disable dual issue  <a href="unionACTLR__Type.html#ab938c32e10162d06ba6b02400e955e01">More...</a><br /></td></tr>
<tr class="separator:a48784073516f219c76ac50a89973dc78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00823a9d14d51b1d277e95916eaf9302"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a00823a9d14d51b1d277e95916eaf9302">b</a></td></tr>
<tr class="memdesc:a00823a9d14d51b1d277e95916eaf9302"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A7.  <br /></td></tr>
<tr class="separator:a00823a9d14d51b1d277e95916eaf9302"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76afcc58dc1393b80755b0c2bb0cc896"><td class="memItemLeft" >struct {</td></tr>
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<tr class="memdesc:a759b38097a34b575141ace0dc26ced8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast  <a href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">More...</a><br /></td></tr>
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<tr class="separator:a26e7a59a65c5e05e1d83921d1e3e7fad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2aae6b9f3b12894f4a615c095a6a889"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:ae2aae6b9f3b12894f4a615c095a6a889"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 6 Enables coherent requests to the processor  <a href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">More...</a><br /></td></tr>
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<tr class="memitem:a496c6ca807fbcaf1de2d52cb26e8252b"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">EXCL</a>:1</td></tr>
<tr class="memdesc:a496c6ca807fbcaf1de2d52cb26e8252b"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 7 Exclusive L1/L2 cache control  <a href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">More...</a><br /></td></tr>
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<tr class="memitem:a5b031fc2bf1a3aa91d8ef1ccc8f964c5"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a3f235030777fe4e20477063df416b515">AOW</a>:1</td></tr>
<tr class="memdesc:a5b031fc2bf1a3aa91d8ef1ccc8f964c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 8 Enable allocation in one cache way only  <a href="unionACTLR__Type.html#a3f235030777fe4e20477063df416b515">More...</a><br /></td></tr>
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<tr class="memitem:af1bce3806946b09cbfe1e13859e48458"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c">PARITY</a>:1</td></tr>
<tr class="memdesc:af1bce3806946b09cbfe1e13859e48458"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 9 Support for parity checking, if implemented  <a href="unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c">More...</a><br /></td></tr>
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<tr class="memitem:a76afcc58dc1393b80755b0c2bb0cc896"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a76afcc58dc1393b80755b0c2bb0cc896">b</a></td></tr>
<tr class="memdesc:a76afcc58dc1393b80755b0c2bb0cc896"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access on Cortex-A9.  <br /></td></tr>
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<tr class="memitem:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#ac65c09d839f8a78340c3b81d3bc90e4d">w</a></td></tr>
<tr class="memdesc:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Bit field declaration for ACTLR layout. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a3f235030777fe4e20477063df416b515" name="a3f235030777fe4e20477063df416b515"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3f235030777fe4e20477063df416b515">&#9670;&#160;</a></span>AOW</h2>

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<p>bit: 8 Enable allocation in one cache way only </p>

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<p>Structure used for bit access on Cortex-A5. </p>

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<p>Structure used for bit access on Cortex-A7. </p>

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<p>Structure used for bit access on Cortex-A9. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac8ac735e3001442e581ae37e773b5929">&#9670;&#160;</a></span>BP</h2>

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<p>bit:16..15 Branch prediction policy </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad1a121373ae8df19f6d11bde3b3ba9c9">&#9670;&#160;</a></span>BTDIS</h2>

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<p>bit: 18 Disable indirect Branch Target Address Cache (BTAC) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a19e5f8f1a2ad8634619399b4eb50a449">&#9670;&#160;</a></span>DBDI</h2>

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<p>bit: 28 Disable branch dual issue </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab938c32e10162d06ba6b02400e955e01">&#9670;&#160;</a></span>DDI</h2>

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<p>bit: 28 Disable dual issue </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4fe04e95b26e089642bee6952f223f82">&#9670;&#160;</a></span>DDVM</h2>

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<p>bit: 15 Disable Distributed Virtual Memory (DVM) transactions </p>

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<h2 class="memtitle"><span class="permalink"><a href="#acfabc61e73fb846970cd6541c5baf7d8">&#9670;&#160;</a></span>DODMBS</h2>

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<p>bit: 10 Disable optimized data memory barrier behavior </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad8faaa57629f258c6eba678ba8efc9da">&#9670;&#160;</a></span>DWBST</h2>

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<p>bit: 11 AXI data write bursts to Normal memory </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a10c6d649f67d6ca9029731fc44631e91">&#9670;&#160;</a></span>EXCL</h2>

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<p>bit: 7 Exclusive L1/L2 cache control </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a55b8e4dd5312f32237dd023032618781">&#9670;&#160;</a></span>FW</h2>

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<p>bit: 0 Cache and TLB maintenance broadcast </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5464ac7b26943d2cb868c154b0b1375c">&#9670;&#160;</a></span>L1PCTL</h2>

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<p>bit:13..14 L1 Data prefetch control </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aacb87aa6bf093e1ee956342e0cb5903e">&#9670;&#160;</a></span>L1PE</h2>

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<p>bit: 2 Dside prefetch </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3800bdd7abfab1a51dcfa7069e245d65">&#9670;&#160;</a></span>L1RADIS</h2>

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<p>bit: 12 L1 Data Cache read-allocate mode disable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a947f73d64ebde186b9416fd6dc66bc26">&#9670;&#160;</a></span>L2RADIS</h2>

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<p>bit: 11 L2 Data Cache read-allocate mode disable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6e8f053d01fb236cc7d002b04d93a19c">&#9670;&#160;</a></span>PARITY</h2>

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<p>bit: 9 Support for parity checking, if implemented </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7921e6e73e0841402a5519f09e6e2ef3">&#9670;&#160;</a></span>RADIS</h2>

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<p>bit: 12 L1 Data Cache read-allocate mode disable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a91288f7320d267d76b4aad4adcf8cda3">&#9670;&#160;</a></span>RSDIS</h2>

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<p>bit: 17 Disable return stack operation </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afa360e0c6bf79094d72bc78fac300149">&#9670;&#160;</a></span>SMP</h2>

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<p>bit: 6 Enables coherent requests to the processor </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac65c09d839f8a78340c3b81d3bc90e4d">&#9670;&#160;</a></span>w</h2>

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<p>Type used for word access. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a67e005f7741b6d46cf95d9c477efef36">&#9670;&#160;</a></span>WFLZM</h2>

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<p>bit: 3 Cache and TLB maintenance broadcast </p>

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